With the smaller sizes and faster operation of electronic equipment in recent years, there have begun to emerge demands for more highly integrated, sophisticated, and faster-running semiconductor devices as well. As a mode for mounting such semiconductor devices, grid array devices, in which leads are arranged across the entire surface of the device in an array shape rather than along the edges, have attracted attention as the mainstream of high-density mounting techniques, and are being further developed. In a grid array-type semiconductor device, ordinarily a wiring board is used to accommodate the demand. This is because by using a wiring board, wiring layers can be stacked in three dimensions so that numerous wires can be provided at high densities; in addition, there is great freedom in wiring layouts, and electrical reinforcement is also facilitated.
One example of a well-known BGA (ball grid array) type semiconductor device is disclosed in Japanese Patent Laid-open No. 6-112354.
In a well-known semiconductor device, as shown in FIG. 17, the semiconductor element 1 is mounted on the joined wiring board 50, and wiring bonding and the metal protrusions of bumps are used to electrically connect the terminals 2 on the semiconductor element 1 with the pads on the conductive lines 5 of the board 50. The wiring board 50 comprises a plurality of wiring layers. Via-holes 6 are provided to enable linking and electrical connection in the perpendicular direction of conductive lines in different wiring layers. Thereafter, resin sealing is performed, and after mounting electrode terminals called solder balls, the joined wiring board 50 is cut into individual boards along the dotted lines 3 in the figure.
The cut portions are the individualized boards shown in FIG. 18A and FIG. 18B. In these figures, 51 and 52 are wiring layers. The pads 9 of the conductive lines 5 are plated in order to secure connectivity. Electrolytic plating is generally used as this plating, due to considerations of cost and processing speed. Hence as shown in FIG. 17, plating leads 8 for electrolytic plating are connected to the conductive lines 5 via the plating stubs 7, and the pads 9 of the electrode tips are plated. Due to the ease of patterning, these plating leads 8 are attached to the wiring of either the uppermost layer or of the lowermost layer. These wiring leads 8 are all connected to the conductive lines 5 in the state of the joined board 50 shown in FIG. 17, and all are electrically short-circuited. But when plating of the pads 9 is completed and the individual boards are cut away, the plating leads 8 are unnecessary for signal transmission, and when the individual conductive lines 5 are short-circuited, signal transmission becomes impossible. Consequently the plating leads 8 are similarly cut away at the time the joined boards 50 are cut along the dotted lines 3, so that the individual conductive lines 5 are electrically independent; but after cutting, plating stubs 7 remain attached to each of the conductive lines as shown in FIG. 18A and FIG. 18B.
In this well-known configuration, the following problems arise.
First, when transmitting signals to various conductive lines 5 of the board, the remaining plating stubs 7 are completely unnecessary for electrical purposes. Further, because electroless plating must be used in order to completely remove them, due to considerations of cost and manufacturing capacity, removal is not practical.
Further problems based on the fact that plating stubs 7 remain are described below.
As the first problem, if the plating stub 7 exists together on the uppermost layer and lowermost layer of the board as shown in FIG. 17 and FIG. 18A, noise may flow into the conductive line 5 connected to this plating stub 7 via the plating stub 7 from the neighboring conductive lines 10 and 11, or noise may enter due to interference between the plating stubs 12 and 13, connected to the conductive lines 10 and 11, and the plating stub 7. Particularly in semiconductor devices using BGA and other wiring boards, often high wiring densities are employed; and because semiconductor devices are moving toward advanced functionality and increasing numbers of input and output terminals, wiring densities will continue to rise, and in addition to these concerns, in future there will inevitably occur such problems as electrical breakdown caused by electrical short-circuits between stubs and by migration. Where signal speeds are concerned also, frequencies may rise and signal amplitudes may decrease, and to this extent devices will be more sensitive to noise, so that the problems are anticipated to become more prominent.
A second problem is the length of the plating stub 7 itself. It is known that in general electromagnetic radiation is released from plating stubs, and this radiation noise causes problems in other signals, such as deformation of waveforms and signal delays. As the speeds of transmitted signals are increased, a plating stub 7 may come to have a capacitance, depending on the frequency and the signal type, with the possibility of adverse effects on signals transmitted over conductive lines; moreover, in impedance matching of a wiring board, unwanted reflections may occur due to the stubs, so that the targeted impedance may not be obtained. Also, unnecessary radiation noise entails energy losses.
No countermeasures whatsoever have been taken to alleviate the concerns with plating stubs in semiconductor devices of the prior art.